The present invention relates generally to semiconductor devices, and more particularly to an epitaxially grown silicon germanium (SiGe) channel FinFET with a silicon (Si) underlayer for a source drain recess etch stop.
Integrated circuit (IC) devices, such as fin field effect transistors (FinFETs), are widely used in logic, memory, processors, and other integrated circuit devices. As the size of the active region of FinFETs continues to decrease, the influence of the source drain region on an electric field or potential in the channel region may increase, known as the short channel effect. Maintaining mobility improvement and short channel control as integrated circuit device dimensions continue to scale down continues to be a challenge in semiconductor device fabrication.